Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors

Authors	Wei W. Xing et al.
Year	2026
Field	Machine Learning
arXiv	2603.13092
PDF	Download
Categories	cs.LG, cs.AR

Abstract

Yield Multi-Corner Analysis validates circuits across 25+ Process-Voltage-Temperature corners, resulting in a combinatorial simulation cost of $O(K \times N)$ where $K$ denotes corners and $N$ exceeds $10^4$ samples per corner. Existing methods face a fundamental trade-off: simple models achieve automation but fail on nonlinear circuits, while advanced AI models capture complex behaviors but require hours of hyperparameter tuning per design iteration, forming the Tuning Barrier. We break this barrier by replacing engineered priors (i.e., model specifications) with learned priors from a foundation model pre-trained on millions of regression tasks. This model performs in-context learning, instantly adapting to each circuit without tuning or retraining. Its attention mechanism automatically transfers knowledge across corners by identifying shared circuit physics between operating conditions. Combined with an automated feature selector (1152D to 48D), our method matches state-of-the-art accuracy (mean MREs as low as 0.11%) with zero tuning, reducing total validation cost by over $10\times$.

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Engineering Breakdown

Plain English

This paper addresses the massive computational burden of circuit yield analysis, which requires simulating designs across 25+ process-voltage-temperature corners with over 10,000 samples per corner—creating O(K×N) cost that becomes prohibitive. The authors identify the 'Tuning Barrier': simple ML models run fast but fail on nonlinear circuits, while sophisticated AI models capture the physics accurately but demand hours of hyperparameter tuning for each new design. They solve this by building a foundation model pre-trained on millions of regression tasks that uses in-context learning to instantly adapt to any circuit without retuning or retraining. The attention mechanism in this foundation model automatically learns to weight relevant circuit features, eliminating the manual engineering of model priors that plagued prior approaches.

Core Technical Contribution

The core novelty is replacing hand-engineered model specifications (engineered priors) with learned priors from a foundation model, enabling zero-shot adaptation to new circuits via in-context learning. Rather than designing circuit-specific architectures or hyperparameters, the model transfers knowledge from pre-training on diverse regression tasks, allowing it to recognize structural patterns in circuit behavior across different operating conditions. The attention mechanism automatically discovers which features matter for prediction in each context, without explicit domain engineering. This is fundamentally different from prior work that either uses fixed mathematical models (fast but inflexible) or requires expensive per-design tuning loops (accurate but slow).

How It Works

The foundation model ingests circuit characterization data formatted as regression examples: inputs describe the circuit topology, corner conditions (process, voltage, temperature), and design parameters; outputs are the predicted performance metrics (delay, power, yield). During pre-training, the model learns patterns across millions of synthetic or real circuit tasks, building generalizable representations of how circuit behavior changes under different conditions. At inference time, for a new circuit, you provide a small set of reference simulations (few-shot examples) as context, and the attention mechanism compares the new circuit structure against these examples, automatically learning how to weight features relevant to this specific design. The model then predicts performance across all 25+ corners without retraining—the in-context learning happens entirely within the forward pass through attention-based computation. The output is a yield prediction or performance estimate for each corner, replacing expensive Monte Carlo simulations.

Production Impact

In production chip design flows, this eliminates the 4-8 hour hyperparameter tuning bottleneck that currently blocks designers from running ML-based yield prediction during early design iterations. Engineers can now run instant corner analysis predictions during synthesis and place-and-route stages, catching yield risks in minutes instead of overnight simulation batches. The approach reduces total simulation cost from O(K×N) full SPICE runs to O(K) forward passes through the foundation model, with amortized cost dropping dramatically when analyzing multiple corners. Trade-offs include: you need a pre-trained foundation model (non-trivial to build; requires millions of training circuits), inference still requires GPU/TPU, and prediction accuracy depends on how well the pre-training distribution matches your design space. Integration is straightforward—the model becomes a plug-in predictor in your CAD flow, replacing or augmenting existing simulation APIs.

Limitations and When Not to Use This

The paper assumes access to a high-quality foundation model pre-trained on representative circuits, which may not exist off-the-shelf for specialized technologies (e.g., analog, RF, power management domains) or cutting-edge process nodes where training data is scarce. In-context learning quality degrades if the new circuit is far outside the pre-training distribution, so the method works best when your design library resembles the foundation model's training data. The paper does not discuss failure modes when circuits exhibit non-monotonic yield behavior, multi-modal distributions, or failure mechanisms not present in training data. Generalization to designs with dramatically different topologies (e.g., analog vs. digital) is unclear, and the approach likely requires domain-specific re-training or fine-tuning for major design paradigm shifts, contradicting the 'zero-tuning' claim for genuinely novel circuit types.

Research Context

This work builds on the recent surge in foundation models for domain-specific regression—extending ideas from large language models (few-shot in-context learning) to the circuit design and EDA domain. It directly addresses a long-standing pain point in statistical circuit analysis, where methods like Monte Carlo sampling and response surface modeling have dominated but hit accuracy-cost trade-offs. The paper likely benchmarks against prior ML approaches for yield prediction (neural networks, random forests, Gaussian processes) and traditional analytical methods. It opens a research direction around foundation models for CAD/EDA, potentially enabling similar instant adaptation for other simulation-heavy tasks like power analysis, thermal modeling, and reliability prediction across the design flow.

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